1. Field of The Invention
This invention relates to error detection apparatus and more particularly to apparatus utilized to check the proper functioning of an associative directory or translator.
2. Environment of Invention
Incorporated by reference herein is U.S. Pat. 3,248,702 entitled "Electronic Digital Computing Machines" by T. Kilburn et al and which is assigned to the assignee of the present invention. This patent discloses a storage hierarchy in which address translation is required to control the transfer of blocks of data from a slow, high-capacity drum store to a fast, low-capacity core memory. At any one time, the high speed core memory can store only 16 blocks of data, whereas the drum store can accommodate 2.sup. 9 blocks of data. Sixteen associative compare registers, each associated with a particular one of the 16 blocks of core storage, retain the 9 address bits which identify the particular one of the 2.sup.9 blocks of data presently being stored in the associated block of core memory. As each request for data by a processor is made, the 9 high order address bits are utilized in a compare operation. This determines whether or not any of the associative registers contain the same address bits, indicating that the requested data is in the core memory. A compare identifies a particular one of the associative registers, the identity of the register being utilized by an encoder to generate 4 address bits utilized to address the particular one of the 16 blocks in the core memory containing the requested data.
When the nine high order address bits of requested data do not match with any address bits in the 16 associative compare registers, a technique must be provided for determining which of the 16 blocks of data in the core memory must be replaced with the requested data. Therefore, also incorporated by reference in this application is U.S. Pat. No. 3,217,298 entitled "Electronic Digital Computing Machines" by T. Kilburn et al and also assigned to the assignee of this application. This patent discloses a technique for determining the particular one of the 16 blocks of data in the core memory to be replaced by requested data not presently stored in the core memory.